In the prior art, an ASIC (application-specific integrated circuit) implemented a deinterleaving operation using multiple Random Access Memories (RAMs) and two parallel deinterleaving chains to keep up with the throughput. Within each of these deinterleaver chains, the received data was first stored into an input RAM in the order it was received. The received data was then read out 1-bit per clock cycle and written into an output RAM at a correct deinterleaved location. The read operation took 64,800 cycles for a 64,800-bit frame regardless of the type of modulation. This required multiple input and output RAMs to buffer the data to keep up with the throughput. The multiple reading and writing operations also introduced latency in the system.